부산대학교 도서관

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 4nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BL×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process[1].