학술논문
Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking
Document Type
Conference
Author
Kobrinsky, M.; Silva, J. D; Mannebach, E.; Mills, S.; El Qader, M. Abd; Adebayo, O.; Radhakrishna, N. Arkali; Beasley, M.; Chawla, J.; Chugh, S.; Clinton, E.; Dasgupta, A.; Desai, U.; De Re, E.; Dewey, G.; Edwards, T.; Engel, C.; Galatage, R.; Ghani, T.; Gudmundsson, V.; Hibbeler, L.; Hicks, J.; Krist, B.; Mehandru, R.; Meric, I.; Morrow, P.; Nandi, D.; Pantuso, D.; Patel, P.; Pawashe, C.; Radosavljevic, M.; Ramamurthy, R.; Samanta, D.; Cekli, S.; Shoer, L.; Amour, A. St; Tan, L. H.; Yemenicioglu, S.; Wang, X.; Wiedemer, J. A.
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
The recent report of a high-yielding process with Back-Side Power Delivery (BSPD) using PowerVia, the benefits obtained on an Intel E-core implementation, and the imminent deployment of PowerVia in High- Volume Manufacturing (HVM), are driving a rapid expansion of R&D across the Si Industry to enable future deployments of this seminal innovation. One such example is the recent experimental demonstration of back-side contacts (BSCONs), which bring about performance and scaling benefits. In this paper, we will identify and discuss potential directions beyond PowerVia, and the key process advances required to enable them. Three key R&D thrusts will be discussed: (i) scaling of the BSPD, (ii) introduction of new functionality on the back-side interconnects stack beyond power delivery, and (iii) efficient device stacking.