부산대학교 도서관

Fixed-Complexity Sphere Decoder (FSD) is an quasi-optimal detector for Multiple-Input Multiple-Output (MIMO) system which is a hardware-friendly parallel tree-search customised to the modulation and antenna scheme employed. However, it is not able to adapt its behaviour for various modulation and antenna schemes, as demanded by modern wireless standard. This restricts its usage in modern adaptive MIMO systems. This paper proposes a solution to this problem. A configurable FSD structure in proposed where normalized higher order modulation schemes can accommodate lower ones. By exploiting clock-gating, FSD of all modulation schemes is equally trimmed to allow power savings of over 30% when implementing on Field Programmable Gate Array (FPGA). This architecture enables the facility to balance the power consumptions with compatible information rate in dynamic, adaptive MIMO communications environments.