학술논문

A Filtering ΔΣ ADC for LTE and Beyond
Document Type
Periodical
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 49(7):1535-1547 Jul, 2014
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Noise
Delays
Bandwidth
Gain
Filtering
Receivers
Noise shaping
A/D converter
channel-select filter
continuous-time
Delta-Sigma modulator (DSM)
filtering A/D converter
low-pass filter
STF
Language
ISSN
0018-9200
1558-173X
Abstract
This paper presents a filtering ADC for the LTE communication standard, where a second-order Delta–Sigma modulator (DSM) is incorporated into the third-order Chebychev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third-order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/ $\sqrt {\rm Hz}$, and an out-of-band (half-duplex) IIP3 of 20/12 dBV rms , with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.