학술논문
Record Performance of 500°C Low-Temperature nMOSFETs for 3D Sequential Integration using a Smart CutTM Layer Transfer Module
Document Type
Conference
Author
Brunet, L.; Reboh, S.; Januel, T.; Garros, X.; Frutuoso, T. Mota; Casse, M.; Sklenard, B.; Brevard, L.; Ribotta, M.; Magalhaes-Lucas, A.; Kanyandekwe, J.; Hartmann, J.-M.; Milesi, F.; Mazen, F.; Acosta-Alba, P.; Kerdiles, S.; Tavernier, A.; Loup, V.; Morales, C.; Larrey, V.; Fournel, F.; Van-Jodin, L. Le; Leforestier, S.; Rolland, E.; Romano, G.; Gaudin, G.; Lugo, J.; Lacord, J.; Maitrejean, S.; Arcamone, J.; Batude, P.; Radu, I.; Fenouillet-Beranger, C.; Andrieu, F.
Source
2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021
Subject
Language
ISSN
2158-9682
Abstract
We report record performances in Top-tier nMOSFETs fabricated by 3D sequential integration, as well as junction optimization guidelines to further optimize the performances within a maximum thermal budget of 500°C. We reached I ON =870µA/µm at I OFF =100nA/µm V DD =1V together with A VT =1.35mV.µm and a decent PBTI lifetime. Moreover, a first generation of Low Temperature LT layer transfer module from Si substrates based on Smart Cut TM was developed to obtain LTSOI quality compatible with 500°C FDSOI process integration: RMS=0.083nm roughness and 0.4nm SOI uniformity. The nMOSFETs fabricated on these LTSOI wafers reached I ON -I OFF performances at 88% of reference transistors integrated on regular SOI wafers.