학술논문
3-D stacked electronics assembly for high-performance imaging detectors
Document Type
Conference
Source
2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515) Nuclear science symposium Nuclear Science Symposium Conference Record, 2003 IEEE. 1:63-67 Vol.1 2003
Subject
Language
ISSN
1082-3654
Abstract
We describe work that extends 3-D patterned overlay high-density interconnect (HDI) to high performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (>90%) optical fill factor, high quantum efficiency, 200 ns inter-frame time interval and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 160-channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. We also briefly review progress in the custom fast image-processing electronics.