학술논문
A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing
Document Type
Conference
Author
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves $9.7 \mu \mathrm{W}$ power/ch and 0.005mm 2 area/ch efficiency with the highest electrode density of 10,000mm -2 , and the fewest interconnects to the authors’ best knowledge.