학술논문
A Reliability Overview of Intel’s 10+ Logic Technology
Document Type
Conference
Author
Grover, R.; Acosta, T.; AnDyke, C.; Armagan, E.; Auth, C.; Chugh, S.; Downes, K.; Hattendorf, M.; Jack, N.; Joshi, S.; Kasim, R.; Leatherman, G.; Lee, S.-H.; Lin, C.-Y.; Madhavan, A.; Mao, H.; Lowrie, A.; Martin, G.; McPherson, G.; Nayak, P.; Neale, A.; Nminibapiel, D.; Orr, B.; Palmer, J.; Pelto, C.; Poon, S. S.; Post, I.; Pramanik, T.; Rahman, A.; Ramey, S.; Seifert, N.; Sethi, K.; Schmitz, A.; Wu, H.; Yeoh, A.
Source
2020 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2020 IEEE International. :1-6 Apr, 2020
Subject
Language
ISSN
1938-1891
Abstract
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.