학술논문
FPGA implementation of fast radix 4 division algorithm
Document Type
Conference
Author
Source
4th IEEE International Workshop on System-on-Chip for Real-Time Applications System-on-chip for real-time applications System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on. :69-72 2004
Subject
Language
Abstract
The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of a fast radix 4 division algorithm (Srinivas and Parthi, 1994) for lookup table based FPGAs implementation. In this algorithm, the quotient digits are determined by observing three most-significant radix 2 digits of the partial remainder and independent of the divisor. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.