부산대학교 도서관

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 Å and ∼8 Å respectively for both n and pMOS devices. The drive currents at I off =100 nA/µm with V DD =1 V is 1.4 mA/µm and 0.6 mA/µm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V T of 0.3/-0.4V, good V T -uniformity, and V T -matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.