부산대학교 도서관

Integrated circuit design rules represent a trade-off between the probability that a given die yields and the physical size of that die. Optimum design rules maximize the average number of good dice on a wafer. This paper presents a methodology for calculating design rules that are optimum in this sense. The development involves four points: (1) Any design rule can be represented physically by a key-and-target structure. (2) Such key-and-target structures lend themselves to suitable mathematical analysis. (3) The average yield of a given ensemble of design rules may be estimated by computer simulation. (4) The most efficient design rules may be estimated by the methods of stochastic optimization.