부산대학교 도서관

In recent years, storage class memory (SCM) has attracted attentions and various R&D results have been reported as it has great potential to improve computing-system performance by filling the latency gap between fast main memories (DRAM) and slow storage (flash memories and hard-drives). SCM's lower cost than DRAMs enables main-memory space in a system to expand dramatically [1]; its faster access time, in comparison to flash memories such as a solid state drive (SSD), can allow it to boost the performance of the main storage system. With an optimized SSD controller in combination with fast flash memory chips (FMCs) with read latency $(t_{\mathrm{R}})$ of $3\mu \mathrm{S}$, the random read latency (RRL) of the SSD system [2] has been improved by $4-10\times$ compared to that of conventional SSDs using high-density 3D flash memories. To boost SSD performance a faster program/erase (P/E) is desired not only to make P/E time shorter but also to improve RRL. When a read command is applied while the previous P/E is executed, the issue of the read should be suspended until completion of the ongoing P/E. Consequently, the faster P/E naturally improves the overall performance of SSDs. In another aspect, narrower distribution of $V_{\mathrm{th}}$ helps to obtain a better RRL because it will reduce the number of read-retries which are issued when the $V_{\mathrm{th}}$ distribution is broader. In this work, we introduce three key techniques for 3D flash memory based SCM in order to improve SSD performance (both RRL and P/E): (1) an enhanced function of suspending and resuming P/E operations to give priority to read operations, (2) a novel programming sequence for making $V_{\mathrm{th}}$ distribution narrower to prevent read fails and read retries, and (3) other techniques including a novel floorplan, employing an external power supply, and an enhanced temperature sensor to improve read/program/verify performances.