학술논문
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
Document Type
Conference
Author
Anders, Jens; Andreu, Pablo; Becker, Bernd; Becker, Steffen; Cantoro, Riccardo; Deligiannis, Nikolaos I.; Elhamawy, Nourhan; Faller, Tobias; Hernandez, Carles; Mentens, Nele; Rizi, Mahnaz Namazi; Polian, Ilia; Sajadi, Abolfazl; Sauer, Mathias; Schwachhofer, Denis; Reorda, Matteo Sonza; Stefanov, Todor; Tuzov, Ilya; Wagner, Stefan; Zidaric, Nusa
Source
2023 IEEE European Test Symposium (ETS) European Test Symposium (ETS), 2023 IEEE. :1-10 May, 2023
Subject
Language
ISSN
1558-1780
Abstract
With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.