학술논문

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 65(3):808-819 Mar, 2018
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Silicon-on-insulator
Transistors
Logic gates
Silicon
Radiation effects
Integrated circuits
Doping
2-D semiconductor
carbon
CMOS
deep submicrometer
FinFET
graphene
MoS2
resistive random access memory (RRAM)
silicon-on-insulator (SOI)
thin film
total ionizing dose (TID)
ultrathin buried oxide (UTBOX)
Language
ISSN
0018-9383
1557-9646
Abstract
From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.