학술논문
A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
Document Type
Conference
Author
Lung, Hsiang-Lan; Miller, Christopher P.; Chen, Chia-Jung; Lewis, Scott C.; Morrish, Jack; Perri, Tony; Jordan, Richard C.; Ho, Hsin-Yi; Chen, Tu-Shun; Chien, Wei-Chih; Drapa, Mark; Maffitt, Tom; Heath, Jerry; Nakamura, Yutaka; Okazawa, Junka; Hosokawa, Kohji; BrightSky, Matt; Bruce, Robert; Cheng, Huai-Yu; Ray, Asit; Ho, Yung-Han; Yeh, Chiao-Wen; Kim, Wanki; Kim, Sangbum; Zhu, Yu; Lam, Chung
Source
2016 IEEE 8th International Memory Workshop (IMW) Memory Workshop (IMW), 2016 IEEE 8th International. :1-5 May, 2016
Subject
Language
Abstract
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.