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Chip package interaction evaluation for a high performance 65nm and 45nm CMOS Technology in a stacked die package with C4 and wirebond interconnections.

Document Type

Article

Author

Muzzy, C.; Danovitch, D.; Gagnon, H.; Hannon, R.; Kinser, E.; McLaughlin, P.V.; Mongeau, G.; Quintal, J.-G.; Sylvestre, J.; Turcotte, E.; Wright, J.

Source

2008 58th Electronic Components & Technology Conference; 2008, p1472-1475, 4p

Subject

Language

Online Access

Full Text (IEEE) Find it@PNU

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