학술논문
Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR
Document Type
Conference
Source
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Integrated Circuits and Microsystems (ICICM), 2021 6th International Conference on. :351-356 Oct, 2021
Subject
Language
Abstract
The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.