학술논문
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis
Document Type
Conference
Author
Source
2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) ISES Smart Electronic Systems (iSES) (Formerly iNiS), 2020 IEEE International Symposium on. :133-138 Dec, 2020
Subject
Language
Abstract
Side-channel attacks can non-invasively extract secret information from hardware devices with a large number of “side-channel” measurements. For example, measuring the dynamic voltage drop of a cryptographic chip can disclose the secret keys by power-noise side-channel emission. To identify the design vulnerabilities and to verify the design countermeasures against side-channel attacks, design time simulation tools are required. However, simulation of these power-noise side-channel emissions are highly complex and computationally intensive due to the scale of the time-domain simulation and the multi-physics models involved.In this paper, we have proposed a fast and comprehensive simulation methodology for the layout based power-noise Side-Channel Leakage Analysis (SCLA). To enable fast dynamic power-noise side-channel emission simulations in time domain, a novel Direct Vector Control (DVC) method is precisely applied to security-sensitive nets to capture all sources of side-channel leakage. Further, we have enabled a location dependent power-noise SCLA to root cause the potential layout design weakness. As a case study, we have validated the proposed SCLA methodology on a test chip which has two 128-bit AES ASIC implementations (CMOS based standard-cell logic and Wave Dynamic Differential Logic (WDDL)) embedded in it. Both Simulation results in terms of measurement-to-disclosure (MTD) have been correlated with silicon measurements to demonstrate the accurate detection of side-channel leakage by our simulation framework.