부산대학교 도서관

This paper presents a power-efficient 12-bit zero-crossing based (ZBC) successive-approximation register (SAR)-assisted two-stage pipeline analog-to-digital converter (ADC). The ZBC's error propagation of conventional multiple stage pipeline ADC is solved by using the proposed two-stage pipelined architecture with one residue amplification only. Moreover, to avoid the signal polarity dependent overshoot error of ZCB amplification, the adaptive level shifting (ALS) scheme is proposed to provide a constant polarity with a ×3 charge transfer speed improvement compared to the conventional approach. The prototyped ADC is fabricated in 40nm CMOS technology with core area of 0.019mm 2 . At 0.9V supply voltage and 40MS/s Sampling rate with 1MHZ input, the implemented ADC achieves a SNDR of 62.2dB with corresponding ENOB of 10.04 bits. The resulting figure-of-merit (FoM) is 5.6fJ/conversion-step.