학술논문

Si-Backside Side-Channel Leakage Measurement and Simulation
Document Type
Conference
Source
2024 21st International SoC Design Conference (ISOCC) SoC Design Conference (ISOCC), 2024 21st International. :189-190 Aug, 2024
Subject
Components, Circuits, Devices and Systems
Semiconductor device measurement
Voltage measurement
Silicon
Flip-chip devices
Integrated circuit modeling
Substrates
Crypto IC chip
Side-channel attack
Side-chnnel leakage
Flip chip implementation
Chip Power Model
Language
ISSN
2472-9655
Abstract
Integrated circuit (IC) chips equipped with crypto circuits are susceptible to side-channel (SC) attacks that exploit SC information derived from the operation of the crypto circuit to reveal the secret keys. In this paper, we focus on the Si substrate voltage on the backside of the IC chip. The use of flip-chip implementations has led to the emergence of a new threat: direct probing attacks on the Si substrate. In this paper, we present a novel Si-backside voltage simulation method that extends the Chip Power Model (CPM). Furthermore, we analyze the Si-backside voltage and evaluate the SC leakage.