부산대학교 도서관

Aiming at the high reliability debugging needs of the system-on-chip of a RISC- V processor in the embedded field, a hardware debugging system based on the RISC- V debugging protocol is designed and implemented. The system uses JTAG signals to communicate with the debug host, and takes over the processor core control through the debug module, which not only realizes the basic debugging function, but also realizes the program cache execution function and hardware trigger function. In order to reduce the occupation of the pin interface, a two-wire debugging interface is designed. At the same time, the structure of the instruction transmission is optimized, and the instruction bypass transmission function is added to improve the reliability of the debugging system. The hardware debugging system has been verified by software simulation and FPGA prototype, and compared with the debugging systems of other RISC- V processors, and the results show that the hardware debugging system is feature-rich and can meet the functional requirements of debugging.