학술논문

SecHLS: Enabling Security Awareness in High-Level Synthesis
Document Type
Conference
Source
2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) Design Automation Conference (ASP-DAC), 2023 28th Asia and South Pacific. :585-590 Jan, 2023
Subject
Components, Circuits, Devices and Systems
Design automation
Asia
Benchmark testing
Scheduling
Complexity theory
Security
Resource management
High-Level Synthesis
Binding
Security Constraints
Information Leakage
Intermediate Representation (IR)
Language
ISSN
2153-697X
Abstract
In their quest for further optimization, High-level synthesis (HLS) utilizes advanced automatic optimization algorithms to achieve lower implementation time/effort for even more complex designs. These optimization algorithms are for the HLS tools' backend stages, e.g., allocation, scheduling, and binding, and they are highly optimized for resources/latency constraints. However, current HLS tools' backend is unaware of designs' security assets, and their algorithms are incapable of handling security constraints. In this paper, we propose Secure- Hls (SecHLS), which aims to define underlying security constraints for HLS tools' backend stages and intermediate representations. In SecHLS, we improve a set of widely-used scheduling and binding algorithms by integrating the proposed security-related constraints into them. We evaluate the effectiveness of SecHLS in terms of power, performance, area (PPA), security, and complexity (execution time) on small and real-size benchmarks, showing how the proposed security constraints can be integrated into HLS while maintaining low PPA/ complexity burdens.