부산대학교 도서관

During future ITER maintenance operations, sensors and their embarked electronics will be exposed to a hostile and radioactive environment. This paper presents the design of a MGy radiation tolerant 16 bit resolver-to-digital converter (RDC) in 130nm CMOS technology. The RDC features a Type II digital tracking loop, able to track resolvers with speeds up to 300rps, and excitation frequencies up to 4kHz. The RDC uses two integrated ΔΣ-analog-to-digital converters (ADCs) to digitize the resolver outputs. The 16 bit, 10kHz ADCs utilize a correlated double sampling technique to remove radiation induced offset and 1/f-noise. The front-end features a static angular resolution of 16 bits (4.2arcsecrms) and a resolution of 10 bits (6arcminrms) at a rotor speed of 100rps. The circuit has a simulated radiation tolerance exceeding 1MGy. It has the ability to operate under temperatures up to 125°C, and to allow multiplexing with signals from other conventional sensors for compact, robust read-out architectures.