학술논문
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
Document Type
Conference
Author
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
Pianissimo is a sub-mW class inference accelerator that adaptively responds to the changing edge environmental conditions with a progressive bit-by-bit datapath architecture. SWHW cooperative control with the custom RISC and the HW counters allows Pianissimo adaptive/mixed precision and block skip, providing a better accuracy-computation tradeoff for low-power edge AI. The 40 nm chip, with 1104 KB memory, dissipates 793-1032$\mu$W at 0.7 V on MobileNetVl, achieving 0. 49-1.25TOPS/W at this ultra-low power range.