학술논문

Triggering and clocking architecture for mixed signal test
Document Type
Conference
Source
Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) International test conference Test Conference, 1998. Proceedings., International. :496-499 1998
Subject
Components, Circuits, Devices and Systems
Signal Processing and Analysis
Power, Energy and Industry Applications
Clocks
System testing
Logic testing
Sampling methods
Automatic testing
Adders
Integrated circuit testing
Jitter
Frequency synchronization
Signal resolution
Language
ISSN
1089-3539
Abstract
A new architecture and its implementation for triggering and clocking functions in a mixed signal tester with flying adder based digital tester periods and an asynchronous, variable frequency clock for mixed signal testing is presented. The approach discussed in the paper offers a solution for very precise edge placement, with a high degree of resolution of the sourcing and sampling clocks with respect to a digital event.