부산대학교 도서관

Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-speed operation. Several researchers have studied a synthesis method based on the Binary Decision Diagram (BDD), as BDD-based optical logic circuits can take advantage of the light speed. However, a fundamental disadvantage of BDD-based optical logic circuits is high power consumption. To address this issue, we propose a variable ordering algorithm for minimizing the power consumption. To the best of our knowledge, this is the first study of an optimization method of BDDs for optical logic circuits. In this paper, we demonstrate that the power consumption largely depends on the variable order of a BDD; however, an optimization problem of finding the variable order to minimize the power consumption has large time complexity. To reduce the execution time, our algorithm utilizes an efficient reordering method based on adjacent variable swap. Experimental results using 10-input logic functions obtained by applying an LUT technology mapper to an ISCAS’85 c7552 benchmark circuit demonstrate that our algorithm can reduces the power consumption by an average of 30% within a reasonable amount of time compared to the results of variable orders that minimize the number of nodes.