학술논문
A 1.25 MS/s Two-Step Incremental ADC With 100-dB DR and 110-dB SFDR
Document Type
Periodical
Author
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 1(11):207-210 Nov, 2018
Subject
Language
ISSN
2573-9603
Abstract
This letter presents a two-step incremental analog-to-digital converter (IADC) with extended counting. The proposed IADC has only one active integrator in the two-step conversion cycle. To achieve high accuracy without trimming or calibration, a cyclic analog-to-digital converter (ADC) with a 31-level quantizer is used in the second step. The ratio of the amplification in the second step is 2.25 (> 2), which leads to exponential resolution improvement by 2.25 8 in 8 cycles. Fabricated in 0.18- $\boldsymbol \mu \text{m}$ CMOS process, the prototype ADC occupies 0.72 mm 2 . With a 55-MHz clock, the measured dynamic range and the SFDR are 100 dB and 110 dB, respectively, at a conversion rate of 1.25 MS/s. The power consumption is 27.7 mW from a 3-V power supply. This gives a Schreier FoM of 173.6 dB.