학술논문
A 1.2V, 78dB HDSP ADC with 3.1V input signal range
Document Type
Conference
Author
Source
2010 IEEE Asian Solid-State Circuits Conference Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian. :1-4 Nov, 2010
Subject
Language
Abstract
A low power, high resolution two-step hybrid delta-sigma/pipelined modulator (HDSP) is presented. The feedback architecture of the HDSP modulator is modified to allow higher orders of noise shaping. The pipelined quantizer is simplified. Finally, the input signal range of the HDSP modulator is extended beyond the supply voltage. The prototype chip is implemented in a 0.18/im CMOS process. With a 1.56 MHz bandwidth, 2.6 mW analog power consumption and 1.2 V analog supply voltage, the measured dynamic range and SNDR of this prototype IC are 78dB and 75dB.