학술논문

MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 32(2):396-400 Feb, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Ray tracing
Pipelines
Hardware
Computer architecture
Parallel processing
Task analysis
Graphics
computer graphics
domain-specific architecture
parallel
ray tracing
Language
ISSN
1063-8210
1557-9999
Abstract
Ray tracing has been regarded as the future of graphics rendering technology for a long time. However, interactive ray tracing still faces challenges, especially in mobile devices, such as high computational intensity and multiple branches. In this brief, we aim to maximize overall efficiency by leveraging all forms of potential parallelism, including task, basic block, loop, and pipeline levels. We present multilevel parallel ray tracing accelerator (MPRTA), an innovative mobile accelerator that offers high performance and optimal efficiency for ray tracing. Experimental results indicate that MPRTA is $1.67\times $ more efficient than the currently best-reported mobile accelerator.