학술논문

Parallel deblocking filter for H.264 AVC/SVC
Document Type
Conference
Source
2010 IEEE Workshop On Signal Processing Systems Signal Processing Systems (SIPS), 2010 IEEE Workshop on. :116-121 Oct, 2010
Subject
Signal Processing and Analysis
Computer architecture
Pixel
Hardware
Throughput
Logic gates
Encoding
Parallel processing
deblocking filter
parallel architecture
Language
ISSN
1520-6130
2162-3562
2162-3570
Abstract
This paper presents a parallel and scalable solution for adaptive deblocking filtering in H.264/AVC. While traditionally in deblocking filtering, the edges in a macroblock are processed in a sequential order, this paper demonstrates how algorithm modifications can be used to enable processing multiple consecutive edges at the same time. The proposed method increases the throughput in proportion to the number of edges that are being processed simultaneously without affecting the PSNR and bit-rate. Details of the method to process 2 consecutive edges in parallel as well as extensions to process 4 and 8 consecutive edges, are provided. A dedicated hardware architecture to process 2 edges is presented along with synthesis results. The architecture achieves a 2× increase in throughput at the expense of a 2.2× increase in area and a 1.23× increase in power.