학술논문
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology
Document Type
Conference
Author
Naso, G.; Botticchio, L.; Castelli, M.; Cerafogli, C.; Cichocki, M.; Conenna, P.; D'Alessandro, A.; Santis, L. De; Cicco, D. Di; Francesco, W. Di; Gallese, M.L.; Gallo, G.; Incarnati, M.; Lattaro, C.; Macerola, A.; Marotta, G.; Moschiano, V.; Orlandi, D.; Paolini, F.; Perugini, S.; Pilolli, L.; Pistilli, P.; Rizzo, G.; Rori, F.; Rossini, M.; Santin, G.; Sirizotti, E.; Smaniotto, A.; Siciliani, U.; Tiburzi, M.; Meyer, R.; Goda, A.; Filipiak, B.; Vali, T.; Helm, M.; Ghodsi, R.
Source
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. :218-219 Feb, 2013
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
We develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.