학술논문
3DVLSI with CoolCube process: An alternative path to scaling
Document Type
Conference
Author
Batude, P.; Fenouillet-Beranger, C.; Pasini, L.; Lu, V.; Deprat, F.; Brunet, L.; Sklenard, B.; Piegas-Luce, F.; Casse, M.; Mathieu, B.; Billoint, O.; Cibrario, G.; Turkyilmaz, O.; Sarhan, H.; Thuries, S.; Hutin, L.; Sollier, S.; Widiez, J.; Hortemel, L.; Tabone, C.; Samson, M-P; Previtali, B.; Rambal, N.; Ponthenier, F.; Mazurier, J.; Beneyton, R.; Bidaud, M.; Josse, E.; Petitprez, E.; Rozeau, O.; Rivoire, M.; Euvard-Colnat, C.; Seignard, A.; Fournel, F.; Benaissa, L.; Coudrain, P.; Leduc, P.; Hartmann, J-M.; Besson, P.; Kerdiles, S.; Bout, C.; Nemouchi, F.; Royer, A.; Agraffeil, C.; Ghibaudo, G.; Signamarcheix, T.; Haond, M.; Clermidy, F.; Faynot, O.; Vinet, M.
Source
2015 Symposium on VLSI Technology (VLSI Technology) VLSI Technology (VLSI Technology), 2015 Symposium on. :T48-T49 Jun, 2015
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.