학술논문
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator
Document Type
Conference
Source
2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2022 IEEE 65th International Midwest Symposium on. :1-4 Aug, 2022
Subject
Language
ISSN
1558-3899
Abstract
In this paper, we describe an MTJ} (magnetic tunnel junction)-based nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU with an accelerator can efficiently perform intermittent operations by incorporating its control as one of the custom instructions in the instruction set, which is suitable for energy-efficient IoT (internet-of-things) applications. Through the performance evaluation of the CPU in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 58% of energy consumption compared to that of conventional approaches with the same CPU and accelerator.