학술논문
VLSI improvements in a binary multiplier based on analog digits
Document Type
Conference
Author
Source
Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020) Signals, systems and computers Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on. 2:1220-1223 vol.2 1999
Subject
Language
ISSN
1058-6393
Abstract
The overlap resolution number system (ORNS) employs digit level residue arithmetic with analog digits. A binary multiplier based on analog digits consists of an array of current-mode CMOS module adders and digit refreshment circuits. The multiplier architecture allows for arbitrary digital accuracy. Despite the simplicity of current mirrors in CMOS circuits. The overall complexity of the multiplier is chiefly determined by the parameters of the binary interface. Its speed is determined by the elementary adder circuits and by digit refreshment circuits. This paper addresses the speed limitations of the existing correction circuit, and proposes a novel design.