학술논문

A 700mV low power low noise implantable neural recording system design
Document Type
Conference
Source
2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society Engineering in Medicine and Biology Society (EMBC), 2014 36th Annual International Conference of the IEEE. :6557-6560 Aug, 2014
Subject
Bioengineering
Noise
Power demand
Gain
Bandwidth
Educational institutions
Pipelines
Power measurement
Neural signal
low-power low-noise design
Neural amplifier
Pipelined ADC
subthreshold operation
smart RFID
Language
ISSN
1094-687X
1558-4615
Abstract
A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identification (RFID) is presented in this paper. A two stage neural amplifier and 8 bit Pipelined Analog to Digital Converter (ADC) are integrated in this system. The optimized number of amplifier stages demonstrates the minimum power and area consumption; The ADC utilizes a novel offset cancellation technique robust to device leakage to reduce the input offset voltage. The neural amplifier and ADC both utilize 700mV power supply. The midband gain of neural amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μVrms and 1.90 respectively. The ADC achieves 8 bit accuracy at 16Ksps with an input voltage of ±400mV. Combined simulation and measurement results demonstrate the neural recording interface's suitability for in situ neutral activity recording.