학술논문
Abstraction and optimization of consistent floorplanning with pillar block constraints
Document Type
Conference
Author
Source
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Design automation Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific. :19-24 2004
Subject
Language
Abstract
We aim at developing floorplan method, a key in topdown design of system LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length.