학술논문

Optimizing energy consumption and parallel performance for static and dynamic betweenness centrality using GPUs
Document Type
Conference
Source
2014 IEEE High Performance Extreme Computing Conference (HPEC) High Performance Extreme Computing Conference (HPEC), 2014 IEEE. :1-6 Sep, 2014
Subject
Communication, Networking and Broadcast Technologies
Computing and Processing
Graphics processing units
Heuristic algorithms
Parallel processing
Instruction sets
Approximation methods
Power demand
Roads
Language
Abstract
Applications of high-performance graph analysis range from computational biology to network security and even transportation. These applications often consider graphs under rapid change and are moving beyond HPC platforms into energy-constrained embedded systems. This paper optimizes one successful and demanding analysis kernel, betweenness centrality, for NVIDIA GPU accelerators in both environments. Our algorithm for static analysis is capable of exceeding 2 million traversed edges per second per watt (MTEPS/W). Optimizing the parallel algorithm and treating the dynamic problem directly achieves a 6.9× average speed-up and 83% average reduction in energy consumption.