부산대학교 도서관

Reducing design rule check (DRC) violations, subject to meeting performance, area and schedule targets, has always been the key metric for VLSI physical design. In leading-edge technology processes under 7nm, a new pattern-specific form of single-line-open (SLO) DRC violations [11] must be avoided in the final-routed GDS layout. In this work, we propose a new methodology and open-source framework, SLO-ECO, that 1) reduces DRC violations beyond where commercial P&R tools saturate, and 2) actively mitigates SLO violations by performing simultaneous detailed placement and routing optimizations in small switchboxes. Our methodology extracts switchboxes from the entire layout, focusing on SLO and DRC hotspots. These switchboxes are then translated into placement and routing grids for application of a satisfiability modulo theories (SMT) solver to find DRC-free layout solutions. To track the direction of routed metal segments, we utilize OpenDB’s dbWireGraph [18] to sequence the metal segments and generate the initial and ending metal segments at the switchbox boundary. Our pin generation flow, using dbWireGraph’s encoding and decoding APIs, reduces runtime by over 100 × compared to the previous work, CoRe-ECO [4]. We also apply multi-threading based on each SMT switchbox trial. Our experimental studies show that SLO-ECO achieves average wirelength reduction of 0.368%, along with average decrease in both DRC and SLO violations of 45.14%, within an average runtime of 15.64 hours (fully automated) across a suite of open-source benchmarks with between 11K and 70K instances.