학술논문
19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology
Document Type
Conference
Author
Choi, Sungdae; Kim, Duckju; Choi, Sungwook; Kim, Byungryul; Jung, Sunghyun; Chun, Kichang; Kim, Namkyeong; Lee, Wanseob; Shin, Taisik; Jin, Hyunjong; Cho, Hyunchul; Ahn, Sunghoon; Hong, Yonghwan; Yang, Ingon; Kim, Byoungyoung; Yoo, Pilseon; Jung, Youngdon; Lee, Jinwoo; Shin, Jaehyeon; Kim, Taeyun; Park, Kunwoo; Kim, Jinwoong
Source
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. :328-329 Feb, 2014
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
The demand for high-density low-cost NAND-Flash memory devices is growing due to the increase in the NAND-Flash application market such as SSD for tablet PCs and ultra-books as well as conventional mobile applications such as USB drives and digital still cameras. Various approaches to implement high-density NAND Flash with small area have been introduced to address the market. Moving from a single-level cell (SLC) to 2 bits per cell (MLC) or to 3 bits per cell is one of the approaches to increasing memory density with the same die area. Lithographic shrinking with conventional 2D technology is the most mature technology although 3D stacking technologies [1] are being developed.