학술논문

The modified space vector PWM method for three-phase voltage source inverter with AC decoupling circuit
Document Type
Conference
Source
2014 9th IEEE Conference on Industrial Electronics and Applications Industrial Electronics and Applications (ICIEA), 2014 IEEE 9th Conference on. :323-328 Jun, 2014
Subject
Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Geoscience
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Vectors
Switches
Inverters
Space vector pulse width modulation
Topology
Load modeling
AC decoupling circuit
bidirectional switch
dead time
efficiency
leakage current
modified VSI
photovoltaic system
power losses
Space-Vector PWM
three-step switching algorithm
Language
ISSN
2156-2318
2158-2297
Abstract
This paper proposes the modified SVPWM control algorithm for the three-phase voltage source inverter, which consists of traditional six switches voltage source inverter and three bidirectional switches for creating the ac decoupling circuit. This topology has the advantages such as the ability to reduce the overall power losses in inverter system and beside that, to decrease the leakage ground current from PV panel (in case of photovoltaic systems) which is based on the principle of decoupling when the zero space vectors occur. For avoiding shoot-through states between six traditional switches and three bidirectional switches, a delay time has been inserted into switching time. The delay time has been controlled more complex to guarantee THD of output voltage, it's called three-step switching algorithm. In oder to demonstrate the feasibility of this algorithm, the operation of the inverter and the modified SVPWM method is simulated by using Matlab/Simulink software and implemented in the experimental prototype by using FPGA Virtex 5 (Xilinx).