학술논문
A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS
Document Type
Periodical
Author
Source
IEEE Microwave and Wireless Components Letters IEEE Microw. Wireless Compon. Lett. Microwave and Wireless Components Letters, IEEE. 20(7):411-413 Jul, 2010
Subject
Language
ISSN
1531-1309
1558-1764
1558-1764
Abstract
This letter presents, for the first time, a 60 GHz four-channel standard compatible heterodyne frequency synthesizer solution with low-cost reference signal. The presented PLL features a dual-core varactor-based LC cross-coupled voltage-controlled oscillator (VCO). The measured phase noise is $-$80.1 dBc/Hz at 1 MHz offset, and it is limited by the phase noise of the reference signal. The measured output spectrum shows spur suppression higher than 32 dBc. Using the lowest reference frequency to date (27 MHz), the presented PLL is suitable for applications in low cost fully integrated multi-gigabit 60 GHz CMOS radio transceivers.