학술논문
High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks
Document Type
Conference
Author
Esmanhotto, E.; Brunet, L.; Castellani, N.; Bonnet, D.; Dalgaty, T.; Grenouillet, L.; Ly, D. R. B.; Cagli, C.; Vizioz, C.; Allouti, N.; Laulagnet, F.; Gully, O.; Bernard-Henriques, N.; Bocquet, M.; Molas, G.; Vivet, P.; Querlioz, D.; Portal, JM.; Mitra, S.; Andrieu, F.; Fenouillet-Beranger, C.; Nowak, E.; Vianello, E.
Source
2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :36.5.1-36.5.4 Dec, 2020
Subject
Language
ISSN
2156-017X
Abstract
We demonstrate, for the first time, 3D monolithically integrated multiple 1T1R Resistive RAM (RRAM) structure storing up to 3.17 bits per RRAM. We study, using a 4 kb 1T1R array, the impact of the conductance relaxation after Multi-Level Cell (MLC) programming. We show that traditional storage applications may be limited to 2 bits per RRAM due to the overlap between conductance ranges after relaxation. On the other hand, our study concludes that conductance relaxation effect is negligible for Neural Network (NN), allowing the use of nine distinct conductance levels per RRAM (equivalent to 3.17 bits) with minimal inference accuracy loss.