학술논문
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
Document Type
Conference
Author
Brunet, L.; Batude, P.; Fenouillet-Beranger, C.; Besombes, P.; Hortemel, L.; Ponthenier, F.; Previtali, B.; Tabone, C.; Royer, A.; Agraffeil, C.; Euvrard-Colnat, C.; Seignard, A.; Morales, C.; Fournel, F.; Benaissa, L.; Signamarcheix, T.; Besson, P.; Jourdan, M.; Kachtouli, R.; Benevent, V.; Hartmann, J.-M.; Comboroure, C.; Allouti, N.; Posseme, N.; Vizioz, C.; Arvet, C.; Barnola, S.; Kerdiles, S.; Baud, L.; Pasini, L.; Lu, C.-M. V.; Deprat, F.; Toffoli, A.; Romano, G.; Guedj, C.; Delaye, V.; Boeuf, F.; Faynot, O.; Vinet, M.
Source
2016 IEEE Symposium on VLSI Technology VLSI Technology, 2016 IEEE Symposium on. :1-2 Jun, 2016
Subject
Language
ISSN
2158-9682
Abstract
For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.