학술논문
Towards efficient and reliable 300mm 3D technology for wide I/O interconnects
Document Type
Conference
Author
Source
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th. :330-335 Dec, 2012
Subject
Language
Abstract
This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.