부산대학교 도서관

Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below -60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design.