학술논문
Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice.
Document Type
Article
Author
Source
Subject
*CRYSTAL lattices
*METAL oxide semiconductor field-effect transistors
*X-ray imaging
*LARGE scale integration of circuits
*SURFACE topography
*TRANSMISSION electron microscopy
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Language
ISSN
0018-9383
Abstract
Silicon-lattice distortion in the 50-\mum-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn \mu-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45^\circ and -0.25^\circ, respectively, over the \mu-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced \sim1000~MPa of tensile stress and \sim-200~MPa of compressive stress, respectively, over the \mu-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively. [ABSTRACT FROM AUTHOR]