학술논문

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM.
Document Type
Article
Source
IEEE Transactions on Electron Devices. Feb2014, Vol. 61 Issue 2, p379-385. 7p.
Subject
*DYNAMIC random access memory
*INTEGRATED circuits
*YOUNG'S modulus
*RF values (Chromatography)
*ANNEALING of semiconductors
*SEMICONDUCTOR doping
*COMPLEMENTARY metal oxide semiconductors
Language
ISSN
0018-9383
Abstract
The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40-\mum thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30-\mum thickness, but suddenly degraded below 20-\mum thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300^\circC annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300^\circC annealing. [ABSTRACT FROM PUBLISHER]