학술논문
Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs
Document Type
Periodical
Author
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 41(3):317-320 Mar, 2020
Subject
Language
ISSN
0741-3106
1558-0563
1558-0563
Abstract
This manuscript presents a systematic low–frequency noise analysis of inversion–mode vertically stacked silicon n–channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input–referred voltage noise Power Spectral Density at flat–band is lower compared to the data on non–stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.